1. Field of the Invention
The present invention relates to a wiring board on which semiconductor elements are mounted, a semiconductor device in which semiconductor elements are mounted on the wiring board, and a method for manufacturing the same, and more specifically relates to a thin wiring board having excellent high-speed transmission characteristics and mounting reliability, and to a semiconductor device in which the wiring board is used.
2. Description of the Related Art
Electronic devices are rapidly becoming smaller, thinner, and increasingly dense, as recently seen in mobile equipment, and greater thinness, lighter weight, higher density, and other characteristics are needed in wiring boards used in device and semiconductor element mounting due to the increase in the number of terminals associated with higher speeds and functionality of semiconductor elements.
Built-up boards and other boards having through-holes have conventionally been commonly used as wiring boards, but boards having through-holes are thick and are furthermore not suited to high-speed signal transmission due to the presence of through-holes.
Tape boards and other thin boards, on the other hand, are also used, but such boards cannot meet the recent demand for higher density because the methods of manufacturing tape boards limit the wiring layers to one or two layers, and the pattern positioning accuracy is inferior to built-up boards due to considerable shrinkage of the tape material.
Coreless boards have been proposed as a method for improving the problems of these wiring boards. In these boards, a wiring structure body or the like is formed on a support board that has been prepared in advance, the support board is removed or separated after the wiring structure body has been formed, and through-holes are left unformed.
Disclosed in Japanese Laid-open Patent Application No. 2000-323613 is a technique in which a copper plate is used as a support board, a wiring structure is formed on the plate, and the support board is then etched away to obtain a coreless board.
Disclosed in Japanese Laid-open Patent Application No. 05-259639 is a technique in which a stainless steel plate is used as a support board, a wiring structure is formed on the plate, and the support board is then peeled away to obtain a coreless board.
Disclosed in Japanese Laid-open Patent Application No. 2004-200668 is a technique in which a copper foil is used as a support board, a wiring structure is formed and semiconductor elements are mounted on the foil, and the copper foil is etched to obtain a coreless board. Also disclosed in the publication is a semiconductor device in which a semiconductor chip is mounted on the coreless board.
Nevertheless, the wiring boards disclosed in the prior art described above have the following problems. With the techniques disclosed in Japanese Laid-open Patent Application Nos. 2000-323613, 05-259639, and 2004-200668, electrodes disposed on the surface obtained by removing a support board are embedded in an insulation resin, and the surface is smooth. Since the electrode surface on which soldering and connecting are to be performed is smooth, there is a problem in that a metal diffusion layer (alloy layer) between the solder and terminal electrode material is formed along the surface of the electrode, and the connection reliability is reduced because the alloy layer weakens the connection strength. In other words, when stress is applied after a connection is made, cracks are generated in the metal diffusion layer. It is therefore difficult to achieve stable reliability in connection structures in which a smooth electrode is used. Also, since the embedded electrodes are supported by an insulation resin that has a lower modulus of elasticity than an inorganic material, there is a problem in that ultrasonic waves are absorbed during wire-bonding and the bonding characteristics are degraded.